Selective Decoding in Associative Memories Based on Sparse-Clustered Networks

TL;DR

This paper introduces a new hardware architecture for Sparse-Clustered Networks (SCN) that significantly increases storage capacity using a novel data-storage technique and Selective Decoding, without sacrificing error performance.

Contribution

It presents a new hardware design for SCNs with a novel data-storage method and Selective Decoding, achieving two orders of magnitude higher capacity.

Findings

Achieves two orders of magnitude higher capacity than previous SCN architectures.

Maintains error-performance levels despite increased capacity.

Requires only a few extra clock cycles per data access.

Abstract

Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardware approaches have recently been introduced for a new family of associative memories based on Sparse-Clustered Networks (SCN) that show attractive features. These architectures are suitable for implementations with low retrieval latency, but are limited to small networks that store a few hundred data entries. In this paper, a new hardware architecture of SCNs is proposed that features a new data-storage technique as well as a method we refer to as Selective Decoding (SD-SCN). The SD-SCN has been implemented using a similar FPGA used in the previous efforts and achieves two orders of magnitude higher capacity, with no error-performance penalty but with the cost of few extra clock cycles per data access.