Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic

TL;DR

This paper introduces dynamic resistive threshold-logic (DRTL), a low-power, high-performance computing approach using non-volatile resistive memory for weights and thresholds, significantly improving energy efficiency over traditional FPGA designs.

Contribution

The paper presents a novel DRTL design that combines resistive memory with dynamic CMOS latches, enabling energy-efficient, configurable, and high-speed logic operations for programmable computing.

Findings

Over two orders of magnitude energy-delay improvement compared to CMOS FPGA.

Memory-based resistive logic enables compact and configurable logic units.

High-speed dynamic pipelined operation enhances performance.

Abstract

We propose dynamic resistive threshold-logic (DRTL) design based on non-volatile resistive memory. A threshold logic gate (TLG) performs summation of multiple inputs multiplied by a fixed set of weights and compares the sum with a threshold. DRTL employs resistive memory elements to implement the weights and the thresholds, while a compact dynamic CMOS latch is used for the comparison operation. The resulting DRTL gate acts as a low-power, configurable dynamic logic unit and can be used to build fully pipelined, high-performance programmable computing blocks. Multiple stages in such a DRTL design can be connected using energy-efficient low swing programmable interconnect networks based on resistive switches. Owing to memory-based compact logic and interconnect design and highspeed dynamic-pipelined operation, DRTL can achieve more than two orders of magnitude improvement in energy-delay product as compared to look-up table based CMOS FPGA.