First experiences with the Intel MIC architecture at LRZ

TL;DR

This paper shares initial experiences and evaluations of the Intel MIC architecture, specifically the Xeon Phi, highlighting its programming ease with standard techniques and its potential in high-performance computing.

Contribution

It provides early insights into programming and performance of Intel's MIC architecture, marking a significant step in adopting this new HPC accelerator.

Findings

Intel Xeon Phi is programmable with standard parallel techniques.

Initial performance evaluations show promising results.

Ease of programming may accelerate adoption in HPC.

Abstract

With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. In particular GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Trying to overcome these difficulties, Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. In the beginning of 2013, the first production-level cards named Intel Xeon Phi came on the market. LRZ has been considered by Intel as a leading research centre for evaluating coprocessors based on the MIC architecture since 2010 under strict NDA. Since the Intel Xeon Phi is now generally available, we can share our experience on programming Intel's new MIC architecture.