On Characterization of Elementary Trapping Sets of Variable-Regular LDPC Codes

TL;DR

This paper characterizes the structure of elementary trapping sets in variable-regular LDPC codes, linking them to short cycles and providing a search method to identify dominant ETSs that influence error floors.

Contribution

It introduces a simple characterization of dominant ETS classes based on short cycles and proposes a layered superset search algorithm for their identification.

Findings

All non-isomorphic ETS structures for given parameters are identified.

ETSs are characterized as layered supersets of short cycles.

The approach aids in error floor analysis and LDPC code design.

Abstract

In this paper, we study the graphical structure of elementary trapping sets (ETS) of variable-regular low-density parity-check (LDPC) codes. ETSs are known to be the main cause of error floor in LDPC coding schemes. For the set of LDPC codes with a given variable node degree $d_l$ and girth $g$, we identify all the non-isomorphic structures of an arbitrary class of $(a,b)$ ETSs, where $a$ is the number of variable nodes and $b$ is the number of odd-degree check nodes in the induced subgraph of the ETS. Our study leads to a simple characterization of dominant classes of ETSs (those with relatively small values of $a$ and $b$) based on short cycles in the Tanner graph of the code. For such classes of ETSs, we prove that any set ${\cal S}$ in the class is a layered superset (LSS) of a short cycle, where the term "layered" is used to indicate that there is a nested sequence of ETSs that starts from the cycle and grows, one variable node at a time, to generate ${\cal S}$. This characterization corresponds to a simple search algorithm that starts from the short cycles of the graph and finds all the ETSs with LSS property in a guaranteed fashion. Specific results on the structure of ETSs are presented for $d_l = 3, 4, 5, 6$, $g = 6, 8$ and $a, b \leq 10$ in this paper. The results of this paper can be used for the error floor analysis and for the design of LDPC codes with low error floors.