Designing Parity Preserving Reversible Circuits

TL;DR

This paper introduces a systematic method for designing parity-preserving reversible circuits, including algorithms from specifications to parity-preserving designs, supported by theoretical results and extensive experiments.

Contribution

It presents the first systematic approach for parity-preserving reversible circuit design, moving beyond ad hoc methods and providing algorithms and theoretical foundations.

Findings

Effective algorithms for converting specifications to parity-preserving reversible circuits.

Theoretical results underpinning the design approach.

Extensive experimental validation demonstrating the approach's effectiveness.

Abstract

Making a reversible circuit fault-tolerant is much more difficult than classical circuit and there have been only a few works in the area of parity-preserving reversible logic design. Moreover, all of these designs are ad hoc, based on some pre-defined parity preserving reversible gates as building blocks. In this paper, we for the first time propose a novel and systematic approach towards parity preserving reversible circuits design. We provide some related theoretical results and give two algorithms, one from reversible specification to parity preserving reversible specification and another from irreversible specification to parity preserving reversible specification. We also evaluate the effectiveness of our approach by extensive experimental results.