Formal Analysis of Soft Errors using Theorem Proving

TL;DR

This paper introduces a formal, theorem-proving approach for analyzing soft errors in electronic circuits, providing guarantees that traditional simulation methods cannot offer, especially for safety-critical applications.

Contribution

It develops a higher-order logic framework with formalized probabilistic models for analyzing soft errors, enhancing accuracy and reliability over simulation-based methods.

Findings

Successfully modeled soft errors in DRAM sense amplifiers

Demonstrated formal verification of probabilistic properties

Provided a foundation for safety-critical circuit analysis

Abstract

Modeling and analysis of soft errors in electronic circuits has traditionally been done using computer simulations. Computer simulations cannot guarantee correctness of analysis because they utilize approximate real number representations and pseudo random numbers in the analysis and thus are not well suited for analyzing safety-critical applications. In this paper, we present a higher-order logic theorem proving based method for modeling and analysis of soft errors in electronic circuits. Our developed infrastructure includes formalized continuous random variable pairs, their Cumulative Distribution Function (CDF) properties and independent standard uniform and Gaussian random variables. We illustrate the usefulness of our approach by modeling and analyzing soft errors in commonly used dynamic random access memory sense amplifier circuits.