Fast Polar Decoders: Algorithm and Implementation

TL;DR

This paper introduces a high-throughput FPGA implementation of a polar decoder that significantly outperforms previous designs, enabling gigabit-per-second decoding speeds for polar codes.

Contribution

It presents a novel algorithm and hardware architecture for polar decoding that achieves an order of magnitude higher throughput than existing solutions.

Findings

Achieved gigabit-per-second decoding speeds on FPGA

Demonstrated improved hardware efficiency over prior decoders

Validated the approach with practical FPGA implementation

Abstract

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. This work aims to increase the throughput of polar decoder hardware by an order of magnitude relative to the state of the art successive-cancellation decoder. We present an algorithm, architecture, and FPGA implementation of a gigabit-per-second polar decoder.