Minimum d-dimensional arrangement with fixed points
Anupam Gupta, Anastasios Sidiropoulos

TL;DR
This paper studies the d-dimensional arrangement problem with fixed points, providing approximation algorithms, integrality gap bounds, and hardness results, especially for the 2D case and its variants relevant to VLSI design.
Contribution
It introduces approximation algorithms and hardness bounds for the generalized d-dimAP+ problem, extending previous work to fixed points and grid constraints.
Findings
O(k^{1/2} log n)-approximation for 2D d-dimAP+
NP-hardness of approximation within Omega(k^{1/4- ext{epsilon}})
Approximation and integrality gap bounds for grid-constrained variants
Abstract
In the Minimum -Dimensional Arrangement Problem (d-dimAP) we are given a graph with edge weights, and the goal is to find a 1-1 map of the vertices into (for some fixed dimension ) minimizing the total weighted stretch of the edges. This problem arises in VLSI placement and chip design. Motivated by these applications, we consider a generalization of d-dimAP, where the positions of some of the vertices (pins) is fixed and specified as part of the input. We are asked to extend this partial map to a map of all the vertices, again minimizing the weighted stretch of edges. This generalization, which we refer to as d-dimAP+, arises naturally in these application domains (since it can capture blocked-off parts of the board, or the requirement of power-carrying pins to be in certain locations, etc.). Perhaps surprisingly, very little is known about this problem…
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