Low Power Dual Edge-Triggered Static D Flip-Flop

TL;DR

This paper presents a new low power dual-edge triggered flip-flop architecture at 180nm CMOS, achieving significant power savings and efficiency improvements over conventional designs for low power applications.

Contribution

The paper introduces a novel dual-edge triggered flip-flop design that reduces power consumption by up to 48%, outperforming existing designs at the same technology node.

Findings

Power dissipation reduced by up to 48%

Improved power-delay product by up to 42%

Suitable for low power, small area applications

Abstract

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.