CMOS Low Power Cell Library For Digital Design
Kanika Kaur, Arti Noor

TL;DR
This paper presents a new low power CMOS cell library designed for digital systems, utilizing voltage and device scaling, with methods to control leakage current, implemented in TSMC 0.18um and 90nm technologies.
Contribution
It introduces a novel CMOS library optimized for low power consumption through scaling and leakage control, validated with simulations in TSMC technologies.
Findings
Reduced power dissipation through voltage and device scaling
Effective leakage current control methods demonstrated
Library implementation verified with simulation results
Abstract
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two…
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Taxonomy
TopicsLow-power high-performance VLSI design · Advancements in Semiconductor Devices and Circuit Design · VLSI and FPGA Design Techniques
