The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

TL;DR

This paper develops a mathematical model to compare maximum voltage drops in on-chip power networks with different pad arrangements, revealing that equilateral triangular and hexagonal layouts minimize voltage drop.

Contribution

It introduces explicit formulas with error bounds for voltage drop analysis, demonstrating the superiority of equilateral arrangements over traditional square layouts.

Findings

Equilateral arrangements reduce maximum voltage drop compared to square layouts.

Mathematical formulas with error bounds are derived for voltage drop estimation.

Triangular and hexagonal pad layouts outperform traditional configurations.

Abstract

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with findings in the literature and with physical and SPICE models, the equilateral power pad arrangement, independent of the underlying power mesh configuration, is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.