Error Correction for NOR Memory Devices with Exponentially Distributed Read Noise
Daniel L. Miller

TL;DR
This paper introduces a novel error correction scheme for NOR Flash memory that leverages exponential read noise distribution, significantly reducing the output bit error rate without additional redundancy.
Contribution
It proposes a new error protection method for NOR memory using a 4-dimensional coding scheme that does not require redundant cells and demonstrates a specific scaling law for error rates.
Findings
The scheme achieves an OBER scaling law of approximately IBER^{3/2}.
For IBER around 10^{-9}, OBER can be reduced to about 10^{-12}.
The method is effective under exponential read noise conditions typical for NOR Flash.
Abstract
The scaling of high density NOR Flash memory devices with multi level cell (MLC) hits the reliability break wall because of relatively high intrinsic bit error rate (IBER). The chip maker companies offer two solutions to meet the output bit error rate (OBER) specification: either partial coverage with error correction code (ECC) or data storage in single level cell (SLC) with significant increase of the die cost. The NOR flash memory allows to write information in small portions, therefore the full error protection becomes costly due to high required redundancy, e.g. 50%. This is very different from the NAND flash memory writing at once large chunks of information; NAND ECC requires just 10% redundancy. This paper gives an analysis of a novel error protection scheme applicable to NOR storage of one byte. The method does not require any redundant cells, but assumes 5th…
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Taxonomy
TopicsAdvanced Data Storage Technologies · Cellular Automata and Applications · Error Correcting Code Techniques
