Scalable Successive-Cancellation Hardware Decoder for Polar Codes

TL;DR

This paper introduces a scalable hardware decoder architecture for polar codes using successive-cancellation, capable of handling very long codes up to 2^20 bits on FPGA with low complexity.

Contribution

The paper presents a novel scalable hardware decoder architecture for polar codes based on successive-cancellation, enabling implementation for very long codes on FPGA.

Findings

Supports code lengths up to 2^20 on FPGA

Low hardware complexity due to regular structure

Decoding performance approaches theoretical limits

Abstract

Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.