Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator
Leonid Yavits, Amir Morad, Ran Ginosar

TL;DR
This paper proposes a new computer architecture replacing last level cache and SIMD accelerator with an associative processor, offering potential performance and power efficiency improvements based on analytic modeling and simulation.
Contribution
It introduces a novel architecture integrating associative processing for combined data storage and computation, supported by an analytic performance model and simulation analysis.
Findings
Potential performance improvements over conventional architectures
Reduced power consumption demonstrated in simulations
Analytic model supports design evaluation
Abstract
This study presents a novel computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data storage and data processing and provides parallel computational capabilities and data memory at the same time. An analytic performance model of the new computer architecture is introduced. Comparative analysis supported by simulation shows that this novel architecture may outperform a conventional architecture comprising a SIMD coprocessor and a shared last level cache while consuming less power.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Data Storage Technologies · Interconnection Networks and Systems
