A Quantum Physical Design Flow Using ILP and Graph Drawing

TL;DR

This paper introduces a quantum circuit design flow combining ILP scheduling and graph drawing for layout generation, reducing average latency by around 10% in ion trap quantum computing.

Contribution

It presents a novel integrated design flow for quantum circuits that optimizes scheduling and layout generation using ILP and graph drawing algorithms.

Findings

Latency reduced by approximately 11% on benchmark set A.

Latency reduced by approximately 9% on benchmark set B.

Effective for ion trap quantum circuit implementation.

Abstract

Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming (ILP) regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11% for a set of attempted benchmarks and by about 9% for another set of benchmarks compared with the best in literature.