Resource Efficient LDPC Decoders for Multimedia Communication

TL;DR

This paper introduces a resource-efficient LDPC decoder architecture using hierarchical quasi-cyclic matrices, achieving high throughput and image quality in multimedia wireless communication.

Contribution

It presents a novel partially-parallel LDPC decoder architecture with a new code construction technique based on hierarchical quasi-cyclic matrices, enhancing resource efficiency and performance.

Findings

HQC matrices achieve BER close to unstructured random matrices

Decoder implementation on FPGA shows high throughput and low resource usage

JPEG image transmission demonstrates superior image quality with the proposed decoder

Abstract

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix with innovative layering of random sub-matrices. Simulation of a high-level MATLAB model shows that the proposed HQC matrices have bit error rate (BER) performance close to that of unstructured random matrices. The proposed decoder has been implemented on FPGA. It is very resource efficient and provides very high throughput compared to other decoders reported to date. Performance evaluation of the decoder has been carried out by transmitting JPEG images over an AWGN channel and comparing the quality of the reconstructed images with those from other decoders.