Performance and Error Analysis of Knill's Postselection Scheme in a Two-Dimensional Architecture

TL;DR

This paper designs a practical two-dimensional quantum computing architecture based on Knill's postselection scheme, achieving high error thresholds and analyzing its performance under various noise models.

Contribution

It presents a 2D architecture implementation of Knill's postselection scheme with optimized error correction and thresholds, including detailed error analysis and comparisons.

Findings

Achieves a 3.06×10^{-4} error threshold in a 2D local noise model.

Monte Carlo simulations show a pseudo-threshold of about 0.1%.

Thresholds improve with lower memory error rates and smaller tile sizes.

Abstract

Knill demonstrated a fault-tolerant quantum computation scheme based on concatenated error-detecting codes and postselection with a simulated error threshold of 3% over the depolarizing channel. %We design a two-dimensional architecture for fault-tolerant quantum computation based on Knill's postselection scheme. We show how to use Knill's postselection scheme in a practical two-dimensional quantum architecture that we designed with the goal to optimize the error correction properties, while satisfying important architectural constraints. In our 2D architecture, one logical qubit is embedded in a tile consisting of $5\times 5$ physical qubits. The movement of these qubits is modeled as noisy SWAP gates and the only physical operations that are allowed are local one- and two-qubit gates. We evaluate the practical properties of our design, such as its error threshold, and compare it to the concatenated Bacon-Shor code and the concatenated Steane code. Assuming that all gates have the same error rates, we obtain a threshold of $3.06\times 10^{-4}$ in a local adversarial stochastic noise model, which is the highest known error threshold for concatenated codes in 2D. We also present a Monte Carlo simulation of the 2D architecture with depolarizing noise and we calculate a pseudo-threshold of about 0.1%. With memory error rates one-tenth of the worst gate error rates, the threshold for the adversarial noise model, and the pseudo-threshold over depolarizing noise, are $4.06\times 10^{-4}$ and 0.2%, respectively. In a hypothetical technology where memory error rates are negligible, these thresholds can be further increased by shrinking the tiles into a $4\times 4$ layout.