Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes

TL;DR

This paper introduces a memory-efficient method for implementing spatially coupled LDPC decoders using a periodic QC algorithm, optimizing storage and processing speed on FPGA hardware.

Contribution

It presents a novel QC-based construction of SC-LDPC codes optimized for memory efficiency and hardware implementation, with FPGA-based validation.

Findings

Reduced memory requirements for parity-check storage

Achieved faster processing speeds on FPGA

No need for block memory in FPGA implementation

Abstract

In this paper we propose the construction of Spatially Coupled Low-Density Parity-Check (SC-LDPC) codes using a periodic time-variant Quasi-Cyclic (QC) algorithm. The QC based approach is optimized to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for Xilinx FPGA to compare the logic and memory requirements for various approaches. It is shown that the proposed QC SC-LDPC code (with optimization) can be stored with reasonable logic resources and without the need of block memory in the FPGA. In addition, a significant improvement in the processing speed is also achieved.