Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Realization of Digital Signal Processing Functions

TL;DR

This paper introduces a novel reconfigurable DSP array architecture that enhances flexibility, parallelism, and scalability for digital signal processing tasks, validated on Virtex5 FPGA.

Contribution

It presents a new FPGA-based DSP processor with fixed common modules enabling efficient reconfiguration for various functions, improving flexibility over traditional FPGA implementations.

Findings

Validated on Virtex5 FPGA

Offers high flexibility and scalability

Achieves efficient reconfiguration of DSP functions

Abstract

Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers, scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP processor that integrates different filter and transform functions. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.