Physical Modeling And Simulation Of Thermal Heating In Vertical Integrated Circuits

TL;DR

This paper presents a quantitative electro-thermal analysis of vertical integrated circuits, modeling heat generation and dissipation to understand temperature rise issues as dies are stacked.

Contribution

It introduces physically based mathematical models for thermal analysis in vertical ICs, highlighting the temperature increase due to stacking and providing numerical results.

Findings

Vertical ICs increase maximum temperature by 17 Kelvin compared to planar ICs.

3D numerical simulations validate the models and show heat distribution effects.

Stacking dies significantly impacts thermal management in vertical IC design.

Abstract

Interconnect is one of the main performance determinant of modern integrated circuits (ICs). The new technology of vertical ICs places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to the planar ICs, vertical ICs have shorter latencies as well as lower power consumption due to shorter wires. This also increases speed, improves performances and adds to ICs density. The benefits of vertical ICs increase as we stack more dies, due to successive reductions in wire lengths. However, as we stack more dies, the lattice self-heating becomes a challenging and critical issue due to the difficulty in cooling down the layers away from the heat sink. In this paper, we provide a quantitative electro-thermal analysis of the temperature rise due to stacking. Mathematical models based on steady state non-isothermal drift-diffusion transport equations coupled to heat flow equation are used. These physically based models and the different heat sources in semiconductor devices will be presented and discussed. Three dimensional numerical results did show that, compared to the planar ICs, the vertical ICs with 2-die technology increase the maximum temperature by 17 Kelvin in the die away from the heat sink. These numerical results will also be presented and analyzed for a typical 2-die structure of complementary metal oxide semiconductor (CMOS) transistors.