Phase-Priority based Directory Coherence for Multicore Processor
Gongming Li, Hong An

TL;DR
This paper introduces PPB, a phase-priority based cache coherence protocol for multicore processors that reduces transient states and stalls, improving performance and energy efficiency.
Contribution
It proposes a novel cache coherence protocol that decouples transactions using phase messages and integrates priority-based arbitration to enhance multicore system efficiency.
Findings
Reduces unnecessary transient states and stalls by up to 24%.
Achieves a 7.4% speedup in multicore performance.
Lowers energy consumption in on-chip networks.
Abstract
As the number of cores in a single chip increases, a typical implementation of coherence protocol adds significant hardware and complexity overhead. Besides, the performance of CMP system depends on the data access latency, which is highly affected by coherence protocol and on-chip interconnect. In this paper, we propose PPB (Phase-Priority Based) cache coherence protocol, an optimization of modern directory coherence protocol. We take advantage of the observation that transient states occur in directory coherence protocol, resulting in some unnecessary transient states and stalling. PPB cache coherence protocol decouples a coherence transaction and introduces the idea of phase message. This phase is considered as the priority of the message. Additionally, we also add new priority-based arbitrators in on-chip network to support PPB cache coherence protocol. This mechanism in on-chip…
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