Verifying Fixed-Point Digital Filters using SMT-Based Bounded Model Checking

TL;DR

This paper presents a method to verify fixed-point digital filters for overflows, limit cycles, and timing issues using an SMT-based bounded model checker, improving the detection of implementation errors.

Contribution

It introduces a novel verification approach employing ESBMC to analyze fixed-point digital filters directly in C, addressing overflow and noise issues effectively.

Findings

Successfully verified overflows and limit cycles in digital filters

Detected potential design errors in fixed-point implementation

Proved effectiveness of SMT-based model checking for filter verification

Abstract

The implementation of digital filters in processors based on fixed-point arithmetic can lead to problems related to the finite word-length. In particular, the processing of signals in such filters can produce overflows and unwanted noise caused by quantization and round off effect during the accumulative addition and multiplication operations. In this paper, we describe a new approach to verify digital filters using an off-the-shelf bounded model checker called ESBMC, which supports full C/C++ and is based on satisfiability modulo theories solvers. In particular, we are able to verify the occurrence of overflows, limit cycles, and time constraints based on a discrete-time model implemented in C. The experiments show that the proposed approach can be used to verify potential problems in fixed-point implementation of digital filters and it can thus be effective in finding realistic design errors.