Inductively Coupled Plasma etching of amorphous silicon nanostructures over nanotopography using C4F8/SF6 chemistry

TL;DR

This paper investigates ICP etching of amorphous silicon nanostructures over nanotopography using C4F8/SF6 chemistry, optimizing parameters for high selectivity and vertical sidewalls, relevant for advanced transistor applications.

Contribution

It demonstrates controlled ICP etching of a-Si nanostructures over nanotopography with optimized parameters for selectivity and verticality, advancing nanofabrication techniques.

Findings

Achieved etch rates from 20 to 125 nm/min by tuning coil power.

Demonstrated high selectivity (4.3:1) for 20 nm a-Si nanowires over oxide trenches.

Showed the importance of low pressure and surface charging effects in etching nanostructures.

Abstract

Inductively Coupled Plasma (ICP) etching of amorphous silicon (a-Si) nanostructures using a continuous C4F8/SF6 plasma over nanotopography in silicon dioxide (SiO2) is investigated. The coil power of the ICP system is used to tune the a-Si etch rate from 20 to 125 nm/min. The etch rates of a-Si, SiO2 and electroresist are measured depending on the SF6 ratio, platen power and chamber pressure and used to optimize the a-Si:SiO2 etch selectivity. The results on nanostructures show that the presence of an insulating etch-stop layer affects the passivation ratio required to achieve vertical sidewalls. A low pressure is also necessary in order to etch the silicon nanostructure embedded into the oxide nanotrenches to form a highly conformable a-Si nanowire. We argue that both of these behaviors could be explained by surface charging effects. Finally, etching of 20 nm a-Si nanowires that cross 15 nm trenches in oxide with vertical sidewalls and a 4.3:1 a-Si:SiO2 etch selectivity is demonstrated. This etching process can be used in applications where nanotopography is present such as single electron transistors or multigate transistors.