A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

TL;DR

This paper presents a high-throughput FPGA decoder for QC-LDPC convolutional codes, achieving 2.0 Gb/s with excellent error performance, by leveraging the quasi-cyclic structure for efficient memory and pipeline design.

Contribution

The paper introduces a novel FPGA decoder architecture for QC-LDPC convolutional codes that significantly improves throughput using dynamic memory and pipelining techniques.

Findings

Achieves 2.0 Gb/s throughput at 100 MHz clock frequency.

Displays error performance lower than 10^{-13} at Eb/N0 of 3.55 dB.

Efficiently utilizes FPGA embedded memory for high data-rate decoding.

Abstract

This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than $10^{-13}$ at a bit-energy-to-noise-power-spectral-density ratio ($E_b/N_0$) of 3.55 dB.