A Static Analysis Framework for Livelock Freedom in CSP

TL;DR

This paper introduces a static analysis framework for CSP processes that conservatively determines livelock freedom by analyzing process syntax, using BDD and SAT implementations, outperforming traditional model checkers.

Contribution

It presents a novel static analysis method for livelock detection in CSP, with algorithms based on process structure and implementations that outperform existing tools.

Findings

The approach conservatively classifies livelock-free processes.

BDD and SAT-based algorithms outperform FDR in benchmarks.

The method has a low rate of inconclusive results.

Abstract

In a process algebra with hiding and recursion it is possible to create processes which compute internally without ever communicating with their environment. Such processes are said to diverge or livelock. In this paper we show how it is possible to conservatively classify processes as livelock-free through a static analysis of their syntax. In particular, we present a collection of rules, based on the inductive structure of terms, which guarantee livelock-freedom of the denoted process. This gives rise to an algorithm which conservatively flags processes that can potentially livelock. We illustrate our approach by applying both BDD-based and SAT-based implementations of our algorithm to a range of benchmarks, and show that our technique in general substantially outperforms the model checker FDR whilst exhibiting a low rate of inconclusive results.