Hardware Implementation of Algorithm for Cryptanalysis

TL;DR

This paper explores hardware implementations of DES cryptanalysis on FPGA, comparing rolled and unrolled architectures to enhance the speed and efficiency of exhaustive key search.

Contribution

It introduces FPGA-based hardware architectures for DES cryptanalysis, demonstrating the effectiveness of rolled architecture over unrolled for faster exhaustive key search.

Findings

Rolled architecture outperforms unrolled in speed.

FPGA implementation significantly accelerates cryptanalysis.

Hardware approach improves efficiency of DES key search.

Abstract

Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays, building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.