Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

TL;DR

This paper details the characterization and production testing of the FE-I4B pixel readout chip for the ATLAS IBL upgrade, ensuring high performance in high luminosity conditions at the LHC.

Contribution

It presents the fabrication, extensive characterization, and yield analysis of the FE-I4B chip for the ATLAS IBL upgrade, including design choices based on test results.

Findings

Successful wafer-level characterization of FE-I4B chips.

Determination of the IBL powering scheme based on test results.

Preliminary yield and distribution data for production wafers.

Abstract

The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3 x 10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300 fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is described. Preliminary wafer to wafer distributions as well as yield calculations are given.