A Taxonomy of Performance Assurance Methodologies and its Application in High Performance Computer Architectures

TL;DR

This paper introduces a comprehensive taxonomy for performance assurance in high performance microprocessor architectures, covering stages from high level design to silicon validation, and demonstrates its application to Intel architectures.

Contribution

It proposes a novel taxonomy that systematically categorizes performance assurance methods across the product lifecycle stages, incorporating assurance spaces and their correlations.

Findings

Provides detailed insight into performance assurance coverage at each stage.

Applies the taxonomy successfully to literature cases and Intel architectures.

Highlights the novelty of structured assurance methodology in high performance microprocessors.

Abstract

This paper presents a systematic approach to the complex problem of high confidence performance assurance of high performance architectures based on methods used over several generations of industrial microprocessors. A taxonomy is presented for performance assurance through three key stages of a product life cycle-high level performance, RTL performance, and silicon performance. The proposed taxonomy includes two components-independent performance assurance space for each stage and a correlation performance assurance space between stages. It provides a detailed insight into the performance assurance space in terms of coverage provided taking into account capabilities and limitations of tools and methodologies used at each stage. An application of the taxonomy to cases described in the literature and to high performance Intel architectures is shown. The proposed work should be of interest to manufacturers of high performance microprocessor/chipset architectures and has not been discussed in the literature.