Event management for large scale event-driven digital hardware spiking neural networks

TL;DR

This paper presents a new hardware data structure called structured heap queue that enables scalable, efficient event management in large-scale digital hardware spiking neural networks, demonstrated on FPGA with real-time image segmentation.

Contribution

Introduction of the structured heap queue, a pipelined hardware data structure that scales efficiently for event management in large digital hardware SNNs.

Findings

Scales linearly with memory, logarithmically with logic resources, and remains constant in processing time.

Successfully implemented on FPGA for an SNN with over 65,000 neurons and 500,000+ synapses.

Achieves real-time image segmentation at 200 ms per image.

Abstract

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65~536 neurons and 513~184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406$\times$158 pixel image is segmented in 200 ms.