Engineering Nanowire n-MOSFETs at Lg < 8 nm

TL;DR

This paper explores how strain and crystal orientation engineering can modify transport masses in nanowire MOSFETs with channel lengths under 8 nm, aiming to mitigate source-drain tunneling and enhance device performance.

Contribution

It demonstrates that engineering heavier transport masses via strain and orientation can improve ON currents in ultra-scaled nanowire MOSFETs using atomistic quantum transport simulations.

Findings

Heavier transport mass reduces source-drain tunneling.

Strain and orientation effectively engineer transport properties.

Heavier mass improves ON state currents in sub-8 nm MOSFETs.

Abstract

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg<8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON state currents in ultra scaled nanowire MOSFETs.