The failure risk analysis of digital circuits
A.N. Pchelintsev
TL;DR
This paper introduces a method for analyzing the failure risk of asynchronous digital circuits by incorporating time-parameters into Boolean algebra, replacing arithmetic with logical operations.
Contribution
It presents a novel mathematical framework that integrates time-parameters into Boolean algebra for failure risk analysis in digital circuits.
Findings
The method effectively models signal propagation and failure risks.
Application to circuit examples demonstrates practical utility.
Provides a new analytical tool for asynchronous circuit reliability.
Abstract
To analyze the failure risk of asynchronous digital circuits the time-parameter is introduced into the Boolean algebra replacing the arithmetic operations by logical operations. There considered an example of construction of signals passing through the logical elements, using the described below mathematical apparatus.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Physical Unclonable Functions (PUFs) and Hardware Security