Nonsmooth Bifurcations, Transient Hyperchaos and Hyperchaotic Beats in a Memristive Murali-Lakshmanan-Chua Circuit

TL;DR

This paper investigates a memristive Murali-Lakshmanan-Chua circuit, revealing complex bifurcations, chaos, and hyperchaos induced by a memristor and grazing bifurcations, supported by numerical and simulation analyses.

Contribution

It introduces a memristor-based modification to the MLC circuit, analyzing its nonsmooth bifurcations and chaotic behaviors with comprehensive numerical and simulation methods.

Findings

Grazing bifurcations induce chaos and hyperchaos.

The circuit exhibits transient hyperchaos and codimension-5 bifurcation.

Numerical and Multisim simulations confirm complex dynamical behaviors.

Abstract

In this paper, a memristive Murali-Lakshmanan-Chua (MLC) circuit is built by replacing the nonlinear element of an ordinary MLC circuit, namely the Chua's diode, with a three segment piecewise linear active flux controlled memristor. The bistability nature of the memristor introduces two discontinuty boundaries or switching manifolds in the circuit topology. As a result, the circuit becomes a piecewise smooth system of second order. Grazing bifurcations, which are essentially a form of discontinuity induced non-smooth bifurcations, occur at these boundaries and govern the dynamics of the circuit. While the interaction of the memristor aided self oscillations of the circuit and the external sinusoidal forcing result in the phenomenon of beats occurring in the circuit, grazing bifurcations endow them with chaotic and hyper chaotic nature. In addition the circuit admits a codimension-5 bifurcation and transient hyper chaos. Grazing bifurcations as well as other behaviors have been analyzed numerically using time series plots, phase portraits, bifurcation diagram, power spectra and Lyapunov spectrum, as well as the recent 0-1 K test for chaos, obtained after constructing a proper Zero Time Discontinuity Map (ZDM) and Poincare Discontinuity Map (PDM) analytically. Multisim simulations using a model of piecewise linear memristor have also been used to confirm some of the behaviors.