Polynomial-time T-depth Optimization of Clifford+T circuits via Matroid Partitioning

TL;DR

This paper introduces a polynomial-time algorithm for optimizing Clifford+T quantum circuits by reducing T-count and T-depth, considering fault-tolerance constraints, and utilizing ancillae for further improvements.

Contribution

The authors present a novel polynomial-time algorithm that optimizes T-depth and T-count in quantum circuits with fault-tolerance considerations, including ancilla-assisted re-synthesis.

Findings

Up to 65.7% reduction in T-count

Up to 87.6% reduction in T-depth without ancillae

Up to 99.7% reduction in T-depth with ancillae

Abstract

Most work in quantum circuit optimization has been performed in isolation from the results of quantum fault-tolerance. Here we present a polynomial-time algorithm for optimizing quantum circuits that takes the actual implementation of fault-tolerant logical gates into consideration. Our algorithm re-synthesizes quantum circuits composed of Clifford group and T gates, the latter being typically the most costly gate in fault-tolerant models, e.g., those based on the Steane or surface codes, with the purpose of minimizing both T-count and T-depth. A major feature of the algorithm is the ability to re-synthesize circuits with additional ancillae to reduce T-depth at effectively no cost. The tested benchmarks show up to 65.7% reduction in T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7% reduction in T-depth using ancillae.