Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs

TL;DR

This paper demonstrates that interface passivation with an ultrathin Al2O3 layer and EOT scaling in InGaAs nanowire MOSFETs significantly improve device variability and subthreshold performance, advancing their potential for low-power applications.

Contribution

It introduces a novel interface passivation technique using an ultrathin Al2O3 layer and EOT scaling to enhance InGaAs nanowire MOSFET performance and reduce variability.

Findings

Record low subthreshold swing of 63mV/dec at sub-80nm channel length

Significant reduction in device variation due to interface passivation

Successful integration of high-k LaAlO3-based gate stack with EOT of 1.2nm

Abstract

High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5nm) Al2O3 interfacial layer between higher-k and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63mV/dec has been demonstrated at sub-80nm Lch for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.