Sequence Diagram Test Case Specification and Virtual Integration Analysis using Timed-Arc Petri Nets

TL;DR

This paper introduces a formal method for specifying and analyzing component test cases with timing constraints using UML and timed-arc Petri nets, enabling early error detection through virtual integration.

Contribution

It defines a novel approach to transform UML-based test case sequence diagrams into timed-arc Petri nets for virtual integration analysis of component-based systems.

Findings

Effective early error detection in component integration

Successful application to avionic system case study

Formal transformation process from UML to Petri nets

Abstract

In this paper, we formally define Test Case Sequence Diagrams (TCSD) as an easy-to-use means to specify test cases for components including timing constraints. These test cases are modeled using the UML2 syntax and can be specified by standard UML-modeling-tools. In a component-based design an early identification of errors can be achieved by a virtual integration of components before the actual system is build. We define such a procedure which integrates the individual test cases of the components according to the interconnections of a given architecture and checks if all specified communication sequences are consistent. Therefore, we formally define the transformation of TCSD into timed-arc Petri nets and a process for the combination of these nets. The applicability of our approach is demonstrated on an avionic use case from the ARP4761 standard.