Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

TL;DR

This paper introduces a novel 5T CMOS SRAM design that significantly reduces dynamic power consumption and area, suitable for low-power SoC applications, by employing innovative biasing and ground control techniques.

Contribution

The paper presents a new 5T SRAM cell with 13% less area and enhanced power efficiency using unique biasing and ground control methods, outperforming traditional 6T designs.

Findings

~13% area reduction compared to 6T SRAM

Significant reduction in dynamic power consumption

Enhanced performance and reliability in 65nm CMOS

Abstract

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a conventional 6T cell, and features a unique bit-line and negative supply voltage biasing methodology and ground control architecture to enhance performance, and suppress standby leakage power.