Scaling Analysis of Nanowire Phase Change Memory

TL;DR

This paper provides an analysis of nanowire phase change memory scaling, showing how device size reduction impacts energy, speed, and thermal management, with implications for future low-power memory technologies.

Contribution

It offers a comprehensive analytical and numerical comparison of scaling effects in different nanowire PCM operation schemes and proposes heat confinement to reduce energy consumption.

Findings

Device size downscaling reduces energy and increases speed significantly.

Over 90% of operation energy is wasted as thermal flux, which can be mitigated.

Scaling alleviates thermal proximity disturbance, enabling better device performance.

Abstract

This letter analyzes the scaling property of nanowire (NW) phase change memory (PCM) using analytic and numerical methods. The scaling scenarios of the three widely-used NW PCM peration schemes (constant electric field, voltage, and current) are studied and compared. It is shown that if the device size is downscaled by a factor of 1/k (k>1), the peration energy (current) will be reduced by more than k3 (k) times, and the operation speed will be increased by k2 times. It is also shown that more than 90% of operation energy is wasted as thermal flux into substrate and electrodes. We predict that, if the wasted thermal flux is effectively reduced by heat confinement technologies, the energy consumed per RESET operation can be decreased from about 1 pJ to less than 100 fJ. It is shown that reducing NW aspect ratio (AR) helps decreasing PCM energy consumption. It is revealed that cross-cell thermal proximity disturbance is counter-intuitively alleviated by scaling, leading to a desirable scaling scenario.