Faster Quantum Number Factoring via Circuit Synthesis

TL;DR

This paper presents a method to significantly reduce the size and latency of quantum circuits for Shor's factoring algorithm by customizing reversible circuits for modular multiplication, leveraging spectral properties and GCD algorithms.

Contribution

It introduces a novel circuit-synthesis approach that optimizes modular multiplication circuits for quantum factoring, achieving substantial reductions in gate counts and circuit latency.

Findings

Gate counts reduced by 4-5 times

Circuit latency significantly decreased

Empirical results demonstrate improved efficiency

Abstract

A major obstacle to implementing Shor's quantum number-factoring algorithm is the large size of modular-exponentiation circuits. We reduce this bottleneck by customizing reversible circuits for modular multiplication to individual runs of Shor's algorithm. Our circuit-synthesis procedure exploits spectral properties of multiplication operators and constructs optimized circuits from the traces of the execution of an appropriate GCD algorithm. Empirically, gate counts are reduced by 4-5 times, and circuit latency is reduced by larger factors.