A real-time design based on FPGA for Expeditious Error Reconciliation in QKD system

TL;DR

This paper presents a FPGA-based real-time error reconciliation method for high-speed QKD systems, significantly reducing error correction time and disclosed bits to enhance key rate security and efficiency.

Contribution

Introduces a practical FPGA implementation for fast error reconciliation in QKD, outperforming PC-based algorithms in speed and security.

Findings

Demonstrates rapid error reconciliation protocol on FPGA

Reduces disclosed bits to improve security

Achieves faster processing compared to PC algorithms

Abstract

For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper we introduce a practical method for expeditious error reconciliation implemented in a Field Programmable Gate Array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.