A joint communication and application simulator for NoC-based SoCs

TL;DR

This paper introduces JANoCS, a cycle-accurate simulator that jointly models communication and processing in NoC-based SoCs, enabling precise evaluation for application-specific designs.

Contribution

The paper presents JANoCS, a novel joint simulation tool for NoC-based SoCs that integrates communication and application modeling for improved accuracy.

Findings

JANoCS enables cycle-accurate joint simulation.

Case studies demonstrate the importance of joint modeling.

JANoCS effectively captures application-specific communication behaviors.

Abstract

NoCs have become a widespread paradigm in the system-on-chip design world, not only for multi-purpose SoCs, but also for application-specific ICs. The common approach in the NoC design world is to separate the design of the interconnection from the design of the processing elements: this is well suited for a large number of developments, but the need for joint application and NoC design is not uncommon, especially in the application specific case. The correlation between processing and communication tasks can be strong, and separate or trace-based simulations fall often short of the desired precision. In this work, the OMNET++ based JANoCS simulator is presented: concurrent simulation of processing and communication allow cycle-accurate evaluation of the system. Two cases of study are presented, showing both the need for joint simulations and the effectiveness of JANoCS.