Nanomagnetic Logic and Magnetization Switching Dynamics in Spin Torque Majority Gates

TL;DR

This paper models spin torque majority gates, explores various magnetization switching regimes including failures, and compares their speed and efficiency to CMOS adders, highlighting potential for spintronic computing.

Contribution

It introduces a detailed modeling of STMGs, identifies different switching regimes, and evaluates their performance metrics for logic applications.

Findings

Switching time of 3ns at 80μA current

Adder throughput comparable to CMOS technology

Identification of regimes leading to switching failure

Abstract

Spin torque majority gates are modeled and several regimes of magnetization switching (some leading to failure) are discovered. The switching speed and noise margins are determined for STMGs and an adder based on it. With switching time of 3ns at current of 80uA, the adder computational throughput is comparable to that of a CMOS adder.