Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha

TL;DR
This paper introduces a new moduli set selection technique for Residue Number Systems to enhance bit efficiency, enabling the design of a reconfigurable DSP processor with improved performance for high-speed applications.
Contribution
A novel moduli set selection method is proposed, improving bit efficiency and enabling a reconfigurable DSP processor architecture based on RNS.
Findings
The proposed moduli set yields better bit efficiency than existing schemes.
The architecture supports real-time high-speed signal processing.
The method is theoretically validated and demonstrated with examples.
Abstract
Residue Number System (RNS), which originates from the Chinese Remainder Theorem, offers a promising future in VLSI because of its carry-free operations in addition, subtraction and multiplication. This property of RNS is very helpful to reduce the complexity of calculation in many applications. A residue number system represents a large integer using a set of smaller integers, called residues. But the area overhead, cost and speed not only depend on this word length, but also the selection of moduli, which is a very crucial step for residue system. This parameter determines bit efficiency, area, frequency etc. In this paper a new moduli set selection technique is proposed to improve bit efficiency which can be used to construct a residue system for digital signal processing environment. Subsequently, it is theoretically proved and illustrated using examples, that the proposed solution…
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Taxonomy
TopicsCryptographic Implementations and Security · Cryptography and Residue Arithmetic · Parallel Computing and Optimization Techniques
