Trade-off between Settling Time and Jitter in Phase Locked Loop

TL;DR

This paper introduces a new Figure of Merit for PLLs that accounts for settling time, jitter, and power, providing a more comprehensive performance evaluation by analyzing their inherent trade-offs through theoretical and simulation methods.

Contribution

It proposes a novel Figure of Merit for PLLs that includes settling time alongside jitter and power, addressing a gap in current benchmarking standards.

Findings

Trade-off between settling time and jitter analyzed theoretically and via simulations.

Modified Figure of Merit incorporates lock time, power, and jitter for better performance assessment.

Behavioral simulations validate the proposed trade-off analysis and merit modification.

Abstract

Most PLL architectures have inherent trade-off between settling time and jitter. This trade-off is ignored by commonly used Figure of Merit (FoM) for PLL, which considers only jitter and power for benchmarking PLL performance. This work proposes new Figure of Merit for PLL, which considers settling time also as performance parameter, along with jitter and power. In this work, trade-off between settling time and jitter is analyzed in linear/non-linear/hybrid PLLs, theoretically and with behavioral simulations. Then, based on settling time vs. jitter relation obtained, currently used Figure of Merit for PLL is modified to consider all important specifications i.e. lock time, power and jitter.