Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions

TL;DR

This paper introduces a fabrication method for self-aligned graphene FETs with polyethyleneimine doping, significantly reducing access resistance and enhancing electrical performance, applicable across various substrates including quartz.

Contribution

The study presents a novel self-aligned spin-on-doping technique for GFETs that improves device performance and is compatible with different substrate materials.

Findings

2X reduction in access resistance

2.5X improvement in electrical characteristics

High carrier mobility of up to 6,300 cm²/Vs

Abstract

We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO$_2$ substrates have high carrier mobilities of up to 6,300 cm$^2$/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications.