Several AES Variants under VHDL language In FPGA

TL;DR

This paper presents four FPGA implementations of AES encryption variants, including Double AES, AESX, and AES-EXE, focusing on their architectures and performance on Altera devices.

Contribution

It introduces new FPGA architectures for multiple AES variants with on-the-fly key expansion and evaluates their implementation on specific FPGA families.

Findings

Successful implementation of four AES architectures on FPGA

Performance analysis on Altera Cyclone III and Stratix devices

Enhanced encryption options with different AES variants

Abstract

This paper provides four different architectures for encrypting and decrypting 128 bit information via the AES. The encryption algorithm includes the Key Expansion module which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and AES-EXE. These architectures are implemented and studied in Altera Cyclone III and STRATIX Family devices.