
TL;DR
This paper analyzes the combinatorial complexity of 3D floor plans in chip design, providing bounds on the number of possible two-layer mosaic floor plans and contrasting them with simpler variants.
Contribution
It introduces new representations for 3D floor plans, establishes an upper bound on their count, and proves a lower bound specifically for two-layer mosaic floor plans.
Findings
Number of two-layer mosaic floor plans is approximately n^{(1+o(1))n/3}.
Contrasts with exponential counts for corner-free mosaic floor plans.
Provides both upper and lower bounds through representation and randomized construction.
Abstract
A 3D floor plan is a non-overlapping arrangement of blocks within a large box. Floor planning is a central notion in chip-design, and with recent advances in 3D integrated circuits, understanding 3D floor plans has become important. In this paper, we study so called mosaic 3D floor plans where the interior blocks partition the host box under a topological equivalence. We give representations which give an upper bound on the number of general 3D floor plans, and further consider the number of two layer mosaic floorplans. We prove that the number of two layer mosaic floor plans is . This contrasts with previous work which has studied `corner free' mosaic floor plans, where the number is just exponential. The upper bound is by giving a representation, while the lower bound is a randomized construction.
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