Checking the error correction strength of arbitrary surface code logical gates
Thomas J. Milburn, Austin G. Fowler
TL;DR
This paper introduces Nestcheck, a new tool for analyzing topological quantum error correction, specifically to determine the minimum errors needed to cause logical gate failure in surface codes.
Contribution
The paper presents Nestcheck, a novel method for evaluating the error correction strength of arbitrary surface code logical gates.
Findings
Nestcheck can analyze complex topological quantum computations.
It determines the minimum error weight leading to logical failure.
Applicable to various surface code configurations.
Abstract
Topologically quantum error corrected logical gates are complex. Chains of errors can form in space and time and diagonally in spacetime. It is highly nontrivial to determine whether a given logical gate is free of low weight combinations of errors leading to failure. We report a new tool Nestcheck capable of analyzing an arbitrary topological computation and determining the minimum number of errors required to cause failure.
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum-Dot Cellular Automata · Low-power high-performance VLSI design