Trapped charge dynamics in InAs nanowires

TL;DR

This paper investigates the origin of random telegraph noise in InAs nanowire transistors, identifying surface oxide traps as the main source, and suggests surface passivation as a solution to improve device stability.

Contribution

It provides detailed measurements of trap dynamics in InAs nanowires and links these to native oxide defects, offering a pathway to reduce noise through surface treatment.

Findings

Trap times depend on temperature and gate voltage

Traps are located in native oxide layers

Oxide removal can reduce telegraph noise

Abstract

We study random telegraph noise in the conductance of InAs nanowire field-effect transistors due to single electron trapping in defects. The electron capture and emission times are measured as functions of temperature and gate voltage for individual traps, and are consistent with traps residing in the few-nanometer-thick native oxide, with a Coulomb barrier to trapping. These results suggest that oxide removal from the nanowire surface, with proper passivation to prevent regrowth, should lead to the reduction or elimination of random telegraph noise, an important obstacle for sensitive experiments at the single electron level.