Design and Implementation A different Architectures of mixcolumn in FPGA

TL;DR

This paper explores various FPGA architectures for the MixColumns step in AES encryption, aiming to optimize hardware efficiency using VHDL and Altera tools.

Contribution

It introduces different FPGA-based MixColumns architectures for AES, demonstrating their implementation and optimization in VHDL for improved hardware performance.

Findings

Optimized FPGA architectures for MixColumns in AES

Successful implementation using VHDL and Altera Quartus II

Hardware evaluation on Cyclone III devices

Abstract

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.