Decoding billions of integers per second through vectorization

TL;DR

This paper introduces SIMD-BP128 and SIMD-FastPFOR, two novel vectorized schemes that significantly accelerate integer array decoding while maintaining competitive compression ratios, leveraging SIMD instructions for high performance.

Contribution

The paper presents two new vectorized decoding schemes, SIMD-BP128 and SIMD-FastPFOR, which outperform existing methods in speed and compression efficiency.

Findings

SIMD-BP128 is nearly twice as fast as previous schemes.

SIMD-FastPFOR achieves similar compression to state-of-the-art but with twice the decoding speed.

Both schemes leverage SIMD instructions for high-performance integer decoding.

Abstract

In many important applications -- such as search engines and relational database systems -- data is stored in the form of arrays of integers. Encoding and, most importantly, decoding of these arrays consumes considerable CPU time. Therefore, substantial effort has been made to reduce costs associated with compression and decompression. In particular, researchers have exploited the superscalar nature of modern processors and SIMD instructions. Nevertheless, we introduce a novel vectorized scheme called SIMD-BP128 that improves over previously proposed vectorized approaches. It is nearly twice as fast as the previously fastest schemes on desktop processors (varint-G8IU and PFOR). At the same time, SIMD-BP128 saves up to 2 bits per integer. For even better compression, we propose another new vectorized scheme (SIMD-FastPFOR) that has a compression ratio within 10% of a state-of-the-art scheme (Simple-8b) while being two times faster during decoding.